1. Field of the Invention
This invention relates to integrated circuit (IC) fabrication technology, and more particularly, to a method of fabricating a conductive plug, such as a contact plug or a via plug, with a low junction resistance in an integrated circuit.
2. Description of Related Art
High-density integrated circuits, such as VLSI (Very Large Scale Integration) ICs, are typically formed with a multi-level interconnect structure including two or more levels of metallization layers for electrically interconnecting the various components in the integrated circuits. A multi-level interconnect structure includes a base layer of met-allization layer which is electrically connected to the source/drain regions of the MOS transistors formed in the integrated circuit, and at least a second layer of metallization layer which is separated from the base layer of metallization layer by an insulating layer, with the second layer of metallization layer being electrically connected to the base layer of metallization layer via a conductive plug formed in the insulating layer. Still another or more layers of metallization layers can be formed over the second layer of metallization layer to constitute the multi-level interconnect structure.
It is to be noted that, in the literature of IC fabrication, the term "contact plug" customarily refers to a conductive plug that is interconnected between an upper level of metallization layer and a conductive part in the substrate, such as a source/drain region of a MOS transistor, whereas the term "via plug" refers to a conductive plug that is interconnected between an upper level of metallization layer and a lower level of metallization layer. In this specification, the two terms "contact plug" and "via plug" are collectively referred to as "conductive plug".
One drawback to the conventional method for fabricating a conductive plug, however, is that undesired insulative materials exist at the junction between the plug and its connected part, thus resulting in a high junction resistance that causes a high resistance-capacitance (RC) time delay to the signal being transmitted through the plug. This degrades the performance of the resulting IC device.
A conventional method for fabricating a contact plug comprises forming an insulating layer on a provided substrate, performing a photolithography and etching process to form an opening within a insulating layer exposing a part of the substrate, and forming a doped polysilicon layer as a plug in the opening.
One drawback to the foregoing process, however, is that the resistance of the junction between the resulting plug and the substrate undesirably high due to two reasons. First, after the etching process used to form the opening, a small amount of the reactant used in the etching process is left at the bottom of the resulting opening and these remnants are considerably high in electrical resistance. Second, a thin oxide layer grows on the exposed surface of the substrate due to exposure to oxygen through the opening and the oxide layer is also considerably high in electrical resistance. These unwanted insulative materials undesirably increase the junction resistance of the resulting plug, thus causing an RC (resistance-capacitance) delay in the signal being transmitted through the plug. The performance of the resulting IC devices is therefore degraded.